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Home Education Center VHDL 2008

VHDL 2008 training course is a valuable resource that introduces the changes and enhancements added by IEEE Std. 1076-2008. The training is structured in three sections which cover design creation, verification with PSL assertions and functional coverage by means of Open Source Verification Methodology. We describe the features, illustrate them with examples, and show how they improve the language as a tool for design and verification. Wait no more - accelerate your projects with the ultimate language enrichments right away.

Schedule with Dates and Locations
Dates   Locations  
April 10 – 11, 2018
Berlin, Germany
Request for Quote
October 09 – 10, 2018
Munich, Germany Request for Quote

Other dates & locations on request

  • Introduction/Overview
  • History of VHDL2008
  • Limitations of prior version

Major benefits of VHDL 2008
  • Generics enhancements:Generic Types;Generic lists in packages; Generic lists in subprograms; Generic Packages; Generic Subprograms
  • Hierarchical referencing (external names);
  • IP Encryption;
  • Force and Release;
  • Type System Changes: Unconstrained Element types (arrays, records);Resolved Elements;
  • Operations: Array/scalar  Logical Operations ; Array/Scalar Addition Operators; Logical Reduction Operators; Condition Operator; Matching Relational Operators; Maximum and Minimum;Mod and Rem for Physical Types; Shift Operators – extended definition;Strength Reduction and ‘X’ Detection
  • Changes in assignments: Conditional and Selected Assignments (Forcing assignments Variable assignments);Matching Case statements: case?
  • Modeling Enhancements: Signal Expressions in port maps; All signals in sensitivity list – process(all); Reading out-mode ports and parameters; Bit-string literals;
  • Enhanced I/O:To_string functions;Read and Write operations – adds octal and hexadecimal I/O;The Tee procedure – avoid replicated write operations;
  • New and Enhanced packages: Enhanced std_logic_1164 package; Numeric bit and Numeric_std packages; Numeric unsigned packages; Fixed Point Math packages; Floating Point Math packages;Standard package;The Env package;
  • Other changes:New reserved words; Delimited comments; Action on Assertion Violation; Multidimensional Array Alias; Type Conversions; Static Ranges;

Functional Verification . Assertion Based Verification
PSL Property Specification Language:
  • Layers: Boolean ;Temporal ; Properties ;Directives ;Assertion units
  • Assertions vs. Properties
  • The notion of time
  • Operators: Always and never; The next operator; The until and before operators; SERE ;Suffix implication |-> and |=>; Weak and strong SEREs;
  • Vunits: How to associate vunits to VHDL entity/architecture ;How to associate vunits to Verilog modules (if the design contains Verilog modules)

Open Source VHDL Verification Metodology (OSVVM)
  • About OSVVM: What is OSVVM ; Benfits ; Packages ;Getting OSVVM
  • Randomizing using RandomPkg: Random Pkg Overview; Randomizing using IEEE.math_real.uniform ; Symplifying Randomization; Manipulating the Seeds; Basic Randomization; Weighted Randomization; Usage
  • Functional Coverage Using CoveragePkg
    • What is Functional Coverage and Why Do I Need it?
      • What is Functional Coverage?
      • Why can’t just use code coverage?
      • Test done?!
      • Why You Need Functional Coverage
    • Writing Functional Coverage using CoveragePkg
      • Item (Point) Coverage done Manually
      • Basic Item(Point) Coverage with CoveragePkg
      • Cross Coverage with CoveragePkg
    • Intelligent Coverage
    • Basic Bin Description
    • Reporting  Coverage
      • Reporting Bin Results –Write Bin
      • Reporting Coverage Holes – WriteCovHoles
      • Setting Headings - SetName
    • Coverage Goals and Optimization Weights
      • Specifying Coverage Goals – AddBins ,  AddCross and GenBin
      • Selecting Randomization Weights –Set WeightMode
      • Specifying Bin Weight –AddBins, AddCross and GenBin

  • Engineers experienced in VHDL, who intend to maximize their design capabilities
  • Engineers experienced in VHDL that need to enable the creation of advanced verification environments.

  • Master the new design capabilities and apply them on design examples
  • Understand the new verification features and learn how to use them in your environment

Basic knowledge of digital hardware design and good knowledge of VHDL.

The workshop is provided by a German trainer, but can also be held in English on request

Trainings Fee per Person
  • €1.250,00 plus VAT

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