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Home Education Center Verilog for VHDL User

Duration: 2 days

Contact us for details about training at your site

Overview Verilog for VHDL users is a brief introduction to Verilog, targeted at designers with experience in VHDL, and it focuses on the techniques needed for RTL and testbench design. As designs grow more complex and design cycles shrink, design teams resort more and more often to the use of Intellectual Property, to design reuse and to collaboration with other remote teams. This means engineers must become „language neutral“ - that is have solid understanding of both VHDL and Verilog and their associated design techniques. Our course is fast and effective method for experienced VHDL users to understand the differences, as well as the similarities between VHDL and Verilog and also to master those Verilog-specific issues that tend to create hard-to-detect problems (e.g. nonblocking assignments).

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  • Understand the concepts of Verilog and how they differ from VHDL
  • Understand the Verilog-specific techniques for RTL design
  • Learn how to avoid Verilog pitfalls

  • Overview
  • A bit of history
  • RTL
    • Interface & Hierarchy: Modules; Comments; Identifiers; Ports; Module & primitive instances; Array of instances; Hierarchical names
    • Signals: Data types; Port connection rules; Vectors; Arrays; Part selects; Numbers
    • Operators: Arithmetic, logical, equality, relational, bitwise and reduction operators; Concatenation & replication; Shift registers
    • Continuos and Procedural Statements: Continuous assignments; Initial & Always; Blocking & non-blocking statements; If, case, casez and casex statements; Conditional operator; For, repeat, while and forever loops; Disabling named blocks
    • Parameters
    • Compiler directives: `define; `include; Conditional compilation
    • Tasks and functions
    • Coding for synthesis: Describing combinational and registered logic; Latch inference; Blocking assignments in clocked procedures; State machines; full and parallel case; Tristates
    • Timescales
    • Mixed language design
  • Testbench
    • Procedural continuous assignments: Assign and deassign; Force and release
    • Fork & join
    • System tasks: Displaying, monitoring and strobing; File access; Writing to and reading from files; $stop and $finish; $random; Value Change Dump
  • Advanced
    • Compiler directives: `uselib, `reset_all
    • Verilog libraries
    • Gate-level simulation: Back annotation using SDF; Delay types; Specify blocks

Hands-On Labs
Throughout this course, extensive hands-on lab exercises provide you with practical experience using ModelSim PE software.

  • Engineers experienced in VHDL, who intend to design with Verilog, too, or to do mixed-language design
  • Engineers who have already acquired some Verilog knowledge and would like to consolidate and extend it

  • Basic knowledge of digital hardware design and good knowledge of VHDL
  • No prior knowledge of Verilog is needed.

  • German or English

Trainings Fee per Person
  • €1.250,00 plus VAT

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