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Trias Romania
 
 
Home Education Center System Verilog





 
Duration: 3 days

Contact us for details about training at your site


Modern FPGA designs have tremendously advanced in both performance and capacity. Verification of this kind of designs has become a daunting task, especially the validation of the design against the specification and test plan. SystemVerilog provides a comprehensive set of verification tools and is a natural extension to Verilog. It also provides constructs with clearer intent like enumerated types, integrated assertions and higher language constructs which support design hierarchy and Object Oriented Programming. Powerful testbench features allow for more flexible and reusable testbench development, even in the context of a VHDL based design.

This workshop will give an overview about SystemVerilog language and will introduce into new verification methodologies „Assertion Based Verification“, „Constrained Random Generation“ and „Functional Coverage“. The participant will learn how to use these powerful verificatin tools to speed up verification as well as to measure the verification progress and how these methodologies can be naturally applied to the verification of VHDL designs.



 
 
 
Schedule with Dates and Locations
Dates   Locations  
March 21 – 23, 2017 Munich Registration
May 16 – 18, 2017 Frankfurt (Main) Registration
July 18 – 20, 2017 Munich Registration
Dec 5 – 7, 2017 Frankfurt (Main) Registration

Other dates & locations on request




Goals
  • Basic Knowledge to the SystemVerilog language
  • Understand the OOP concept in SystemVerilog
  • Understand how to take advantage of the OOP concept for faster and more efficient, re-usable Testbench design
  • Understand the concept of an automated Testbench
  • Introduction into SystemVerilog Assertions, Constrained Randomization and Functional Coverage and how to integrate these to the Testbenches in a VHDL design context
  • Understand how these concepts help verifying the design more efficiently



 
Agenda
  • Motivation
  • Introduction to SystemVerilog
  • SystemVerilog Assertions
  • Constrained Randomization
  • Functional Coverage



Hands-On Labs
Throughout this course, extensive hands-on lab exercises provide you with practical experience using Questa software.



 
Prerequisites
  •  VHDL or Verilog experience in Verification and Design



Languages
  • German or English (at your request)



Trainings Fee per Person
  • €1.850,00 plus VAT



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