Facebook   Twitter
Solutions & Products
Education Center
System Verilog
VHDL 2008
UVM Made Easy for FPGA Designers
Accelerating FPGA/Digital ASIC Design
Accelerating FPGA VHDL Verification
Signal Integrity
HS Memory Interfaces
Verilog for VHDL User
Web Seminars / Multimedia
Consulting & Services
Technical Support
Events & News
Partner Network
Trias Romania
Home Education Center Signal Integrity

This workshop is aimed at developers who want to implement high-speed interfaces between semiconductor components and who want to design complex high-speed circuits at board level. This Workshop is designed for developers who not only design schematics but also systems and the layout.
You will learn to judge when signal integrity is important and relevant, to interpret, for example, IBIS models, and to select appropriate termination procedures. Signal refection and crosstalk effects are described and demonstrated by simulation. Simulation examples are for typical PCB structures. You will learn how to implement high-speed buses, including clock design, loading and signal termination. Furthermore, the power distribution and bypassing design are main topics.
Detailed discussion of solving potential Signal Integrity problems on high-speed memory interfaces and serial transceiver links (optional modules).

Agenda (2 Day Workshop)
  • Course Introduction
  • Introduction to Signal Integrity
  • Chip-to-Chip Timing:
    Clocking schemes, setup and hold constraints, timing budget, CMOS driver and characteristics, CMOS receiver and characteristics, FPGA interface options.
  • IBIS Models for SI Simulation:
    SI modeling, IBIS model, using IBIS models, SI tools, HyperLynx SI, LAB: simulation example.
  • Transmission Lines:
    Basics, critical trace length, transmission lines, LAB: transmission line parameters
  • Reflection:
    Discussion reflection effect, reflection calculations, rules for solving reflection problems, reflection and circuit topologies, LAB: minimizing reflection
  • Crosstalk:
    Crosstalk effect, crosstalk calculations, rules for solving crosstalk problems, LAB: minimizing crosstalk
  • SI-Analysis on System Level:
    SI analysis methods, simulation elements, system analysis (example clock network, example high-speed parallel interface, example memory interface), LAB: SI analysis memory interface
  • Power Integrity:
    Parameters of power supply networks, power supply decoupling, board level power supply, Demo: solving bypassing with HyperLynx PI
  • Board Layout Guidelines
  • Signal Integrity Measurement Techniques
  • Course Summary

Agenda (Optional 3rd Day of Workshop)
  • Signal Integrity of High-Speed Memory Interfaces:
    Memory interface design challenges (timing parameters and relationships, design requirements, examples)
    Pre-layout analysis: methodology, simulation examples, parameter variation for timing optimization; LAB: Timing analysis on selected nets
    Post-layout analysis: methodology – DDRx Wizard, collecting design parameters, preparing simulation, SI analysis, discussion of results; LAB: Complete SI simulation DDR3 interface
    Design guidelines to overcome potential SI problems on memory interfaces
  • Signal Integrity on Serial Transceiver Links:
    Design challenges for serial links (signal and transmission media characteristics – signal degradation), transceiver modeling
    Procedures to improve SI behavior of serial links (pre-emphasis and equalization)
    Pre-layout analysis: serial link architecture, methodology, parameter optimization to fit design specification; LAB: Serial transceiver link estimation
    Post-layout analysis: methodology to replace estimated parameters by real parameters, LAB: SI analysis of real transceiver link
    Design guidelines to overcome potential SI problems on serial link interfaces

  • Hardware Design and CAD Engineers who will avoid / overcome signal integrity problems on PCBs
  • Familiarity with High-speed PCB concepts

Schedule with Dates and Locations
Dates   Locations  
February 26 – 28, 2018 Munich, Germany Request for Quote
June 11 – 13, 2018 Berlin, Germany
Request for Quote
September 17 – 19, 2018 Munich, Germany Request for Quote
November 12 – 14, 2018 Berlin, Germany
Request for Quote

  • Understand circuit timing relationships
  • Learn basics of IBIS simulation
  • Understand reflection and crosstalk effects on PCBs
  • Learn how to overcome reflection and crosstalk effects
  • Apply for knowledge to more complex circuits

  • 2 days standard workshop or
  • 3 days with additional modules on memory interfaces and serial links (including third day)

Basic knowledge on hardware design

The workshop is provided by a German trainer, but can also be hold in English on request

Trainings Fee per Person
  • €1.250,00 plus VAT for 2-day trainings course
  • €1.850,00 plus VAT for 3-day trainings course

nach oben