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Trias Romania
 
 
Home Education Center HS Memory Interfaces





 
Overview
This workshop is aimed at developers who want to implement high-speed memory interfaces on custom boards. Memory interfaces are used very often, they will be faster and faster – and the design issues are more and more challenging. This Workshop is designed for developers who not only design schematics but also design systems and the layout.

You will learn the memory device specifics relevant for logical and physical design. Timing and voltage margins will be discussed.

You will learn to use signal integrity simulation to optimize high-speed memory interfaces. IBIS models and simulation are used to explain the effects and potential bottlenecks. You will learn how to implement high-speed memory interfaces, including board level design topics.  Furthermore, the power supply issues will be discussed. Finally, you will learn board level verification options.


 
Schedule with Dates and Locations
Dates   Locations  
March 07 – 08, 2017 Stuttgart Registration
June 13 – 14, 2017 Berlin
Registration
Sept 12 – 13, 2017 Stuttgart
Registration
Nov 07 – 08, 2017 Berlin Registration
Agenda
  • Course Introduction

  • Overview Memory Devices
    DDRx, LPDDRx, GDDRx, QDR, RLDRAM (in general and comparison)

  • DDRx Memory Devices Details
    DDR vs. DDR2 vs. DDR3, functionality and specific features, JEDEC standards
    LAB: Memory Device Timing Parameters

  • Memory Controllers
    Memory controller functionality, example standard controller (Intel), examples FPGA based controllers, controller design challenges and solutions
    LAB: Memory Controller Timing Parameters

  • Memory Interface Design
    Logical design, timing, power supply; signal topologies and termination
    LAB: DDR3 Memory Interface

  • Short Introduction to Signal Integrity
    Transmission lines and signal edges; discussion reflection and crosstalk effects, calculations and general rules for solving reflection and crosstalk problems

  • Basics for SI Simulation of Memory Interfaces
    IBIS model, using IBIS models, SI tools, HyperLynx SI
    LAB: Simple Simulation Example

  • SI Simulation Options for Memory Interfaces
    Critical parameters, pre-layout vs. post-layout analysis

  • Improving Design Margins Through Simulation
    Pre-layout analysis: methodology, simulation examples, parameter variation for timing optimization
    LAB: Timing Analysis on Selected Nets

    Post-layout analysis: methodology – DDRx Wizard, collecting design parameters, preparing simulation, SI analysis, discussion of results
    LAB: Complete SI simulation DDR3 interface

  • Verification of Memory Interfaces
    Verification on existing hardware – simulation vs. measurement; Measurement options and solutions
    LAB: Evaluation Measurement Result

  • Memory Interface Guidelines
    Design guidelines to overcome potential SI problems on memory interfaces

  • Course Summary


Audience
  • Hardware Design and CAD Engineers who will design high-speed memory interfaces, especially DDR3 interfaces with data rates above 1 Gbps
  • System Designers


 
Goals
  • Understand memory timing relationships
  • Learn basics of signal integrity and IBIS simulation
  • Learn how to design memory interfaces
  • Run signal integrity simulations to verify memory interfaces in design process
  • Discuss options for hardware verification on existing hardware


 
Prerequisites
Basic knowledge on hardware design


Languages
The workshop is provided by a German trainer, but can also be hold in English on request


Trainings Fee per Person
  • €1.250,00 plus VAT


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