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Home Education Center Accelerating FPGA/Digital ASIC Design

(Learn how basic quality improvement will also reduce development time and allow efficient reuse. HDL language, tool and technology independent. Digital design for FPGA & ASIC.)
Duration: 2 days

Contact us for details about training at your site

We are happy to announce a 2-day course in FPGA-and digital ASIC-design – on how to optimize and accelerate development and at the same time improve the quality of your product.

The course is HDL language, tool and technology independent and focus on the issues that matter the most for efficiency and quality.

Our mission is to give you a good platform for a pragmatic approach to improving your FPGA and ASIC projects!

Digital design for FPGAs and ASICs has a huge improvement potential with respect to development time and product quality.

A lot of time is wasted on inefficient design and lack of awareness and knowledge of the most critical digital design issues. This also seriously affects the quality of the end product. The really good thing is that this huge improvement potential can be realised just by making a few important changes to the way we design.

The most important design related issues to improve are:
  • Design Architecture & Structure
  • Clock Domain Crossing
  • Coding and General Digital Design
  • Reuse and Design for Reuse
  • Timing Closure
  • Quality Assurance - at the right level
Design Architecture and Structure

This is probably the single most important issue with respect to development efficiency and quality. Unfortunately most FPGA modules are not at all properly structured. There is of course always some kind of structure, but seldom even close to a good and efficient structure. This course spends a lot time on some standard bad and a desired good design structuring. Architecture is key at all levels from top level to deep down in the module micro architecture.

A good design structure yields a good overview and understand, easier extendibility and maintainability, and far better modified reuse. A very important side effect is lower power consumption, better frequency performance and a smaller FPGA/ASIC footprint.

Clock Domain Crossing (CDC)

CDC is one of the most error prone areas of digital design. Most designers believe they know how to handle this perfectly well, - but for some strange reason this is still the worst problem in a lot of projects. What we often see is that a CDC was not as trivial as first assumed. There are lots of special cases where you need to know exactly how to handle a specific challenge for a specific technology/device given your specific synthesis and P&R tool. This course looks at general CDC issues and how to handle them, but also looks closer at a lot of special scenarios.

Coding and General Digital Design

Coding style is very individual, and to a certain extent that is acceptable. However, most coding styles are not really acceptable or good enough if you are considering readability, understanding and maintenance, and thus not at all acceptable with respect to efficiency and quality. This course looks at how to write understandable code.

There are some myths and misunderstandings about FSM coding and Reset handling. We will have a closer look at that in this course.

Registers are defined and described multiple places like C header files, HDL design files, HDL Testbench and Documentation. This should really be generated and maintained automatically to save time and keep all parts synchronized. We will show one way of handling this.

Register Wizard is a free tool to handle this in a structured manner. This tool is the only language dependent part of this course as the tool currently only provides VHDL for the FPGA/ASIC design and testbench.

Reuse and Design for Reuse

Actually Reuse and Design for Reuse are two totally different subjects.

The course will look at the following:
  • Design for ‘Plug and Play’ reuse
  • Wrapping for 'Untouched reuse'
  • Design for modified reuse
All of these aspects have different challenges and benefits, and we will go into some detail on that.

Timing Closure

The course will not dive into technology specific optimization, but will look at how performance may be improved by applying a more structured architecture.

Quality Assurance - at the right level

Most quality issues will be covered while discussing architecture, CDC and coding, but the course will also look at how quality may be improved by walk-through, sparring, reviews, check-lists, documentation etc.

In General

There will be a few examples on quite common bad approaches, and more examples on good approaches for architecture, CDC, Coding, Reuse, etc.

Almost all examples are both technology (FPGA/ASIC) and language (VHDL/Verilog/SV) independent.

(There is perhaps an even bigger improvement potential on Verification. This is however covered in a different course 'Accelerating FPGA VHDL Verification'.)


The feedback from previous course participants in Scandinavia has been very good (from designers at all levels, from 1 to 30 years’ experience).

The main focus in this course is quality and efficiency improvement, making you a better designer and your company a better product development organisation.

All slides will be in English.

Quotes from previous courses:
  • The only bad thing about this course - is that we didn't do it earlier
  • An eye opener - Most issues apply directly in our organisation
  • A very good course on very relevant improvement potentials
  • I think the material is need-to- know for every designer
  • The course makes you think through how you and your company are doing things
Target audience and Prerequisites
The course is intended for FPGA designers and Digital ASIC designers who wants to work smarter and more efficiently - and design products with higher quality.

The course participants must have working knowledge of FPGA design or Digital ASIC design. Previous participants have had from 1 year to 30 years experience.
Other Info
This course is complementary to the courses offered by FPGA vendors and tool vendors - and also complementary to more general courses offered by Doulos, Esperan, etc. and various universities. The strong focus on the issues that matter the most for efficiency and quality makes this a good platform for a pragmatic approach to improving your FPGA and ASIC projects.

This course may also be held on-site on request - with a duration of one to three days depending on your starting point and level of ambition. Such a course allows some flexibility and adaptation - and would promote more interaction. Presentation in English.

Please note that the previous course 'FPGA Development Best Practices' is now split into two different courses:
  • Accelerating FPGA and Digital ASIC Design (This course) (Digital Design. Language, tool and technology independent)
  • Accelerating FPGA VHDL Verification (Structured verification with examples from UVVM)
Trainer: Espen Tallaksen

Espen Tallaksen is managing director and founder of BITVIS, the leading design centre for Embedded SW and FPGA in Norway. He has more than 28 years of experience in FPGA/ASIC development.

During twenty years Espen has had a special interest for methodology cultivation and pragmatic efficiency and quality improvement. One result of this interest is the UVVM verification platform that is currently being used by companies world-wide.

He has given many presentations in Scandinavia on various technical aspects of FPGA development -- including:
  • Keynote at FPGAworld
  • Keynote speaker at ABB Embedded Systems Forum
  • Various presentations at FPGAworld
  • ...and many more
Espen is also the initiator and chair of the Norwegian FPGA-forum.
Schedule with Dates and Locations
Dates   Locations  
June 05 – 06, 2018 Munich, Germany Request for Quote
September 25 – 26, 2018 Berlin, Germany Request for Quote
Other dates & locations on request
€1.250,00 plus VAT
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